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HUFA76407DK8
Data Sheet December 2001
3.5A, 60V, 0.105 Ohm, Dual N-Channel, Logic Level UltraFET(R) Power MOSFET Packaging
JEDEC MS-012AA
BRANDING DASH
Features
* Ultra Low On-Resistance - rDS(ON) = 0.090, VGS = 10V - rDS(ON) = 0.105, VGS = 5V
5
1 2 3 4
* Simulation Models - Temperature Compensated PSPICE(R) and SABERTM Electrical Models - SPICE and SABER Thermal Impedance Models - www.fairchildsemi.com * Peak Current vs Pulse Width Curve * UIS Rating Curve
Symbol
SOURCE1 (1) GATE1 (2) DRAIN 1 (8) DRAIN 1 (7)
* Transient Thermal Impedance Curve vs Board Mounting Area * Switching Time vs RGS Curves
SOURCE2 (3) GATE2 (4)
DRAIN 2 (6) DRAIN 2 (5)
Ordering Information
PART NUMBER HUFA76407DK8 PACKAGE MS-012AA BRAND 76407DK8
NOTE: When ordering, use the entire part number. Add the suffix T to obtain the variant in tape and reel, e.g., HUFA76407DK8T.
Absolute Maximum Ratings
TA = 25oC, Unless Otherwise Specified HUFA76407DK8 60 60 16 3.5 3.8 1.0 1.0 Figure 4 Figures 6, 17, 18 2.5 20 -55 to 150 300 260 UNITS V V V A A A A
Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDSS Drain to Gate Voltage (RGS = 20k) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS Drain Current Continuous (TA = 25oC, VGS = 5V) (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID Continuous (TA = 25oC, VGS = 10V) (Figure 2) (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID Continuous (TA = 100oC, VGS = 5V) (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID Continuous (TA = 100oC, VGS = 4.5V) (Figure 2) (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM Pulsed Avalanche Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UIS Power Dissipation (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD Derate Above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG Maximum Temperature for Soldering Leads at 0.063in (1.6mm) from Case for 10s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL Package Body for 10s, See Techbrief TB334. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg NOTES: 1. TJ = 25oC to 125oC. 2. 50oC/W measured using FR-4 board with 0.76 in 2 (490.3 mm2) copper pad at 1 second. 3. 228oC/W measured using FR-4 board with 0.006 in 2 (3.87 mm2) copper pad at 1000 seconds.
W mW/oC oC
oC oC
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
This product has been designed to meet the extreme test conditions and environment demanded by the automotive industry. For a copy of the requirements, see AEC Q101 at: http://www.aecouncil.com/ Reliability data can be found at: http://www.fairchildsemi.com/products/discrete/reliability/index.html. All Fairchild semiconductor products are manufactured, assembled and tested under ISO9000 and QS9000 quality systems certification.
(c)2001 Fairchild Semiconductor Corporation HUFA76407DK8 Rev. B
HUFA76407DK8
Electrical Specifications
PARAMETER OFF STATE SPECIFICATIONS Drain to Source Breakdown Voltage BVDSS IDSS IGSS VGS(TH) rDS(ON) ID = 250A, VGS = 0V (Figure 12) ID = 250A, VGS = 0V , T A = -40oC (Figure 12) Zero Gate Voltage Drain Current VDS = 55V, VGS = 0V VDS = 50V, VGS = 0V, TA = 150oC Gate to Source Leakage Current ON STATE SPECIFICATIONS Gate to Source Threshold Voltage Drain to Source On Resistance VGS = VDS, ID = 250A (Figure 11) ID = 3.8A, V GS = 10V (Figures 9, 10) ID = 1.0A, V GS = 5V (Figure 9) ID = 1.0A, V GS = 4.5V (Figure 9) THERMAL SPECIFICATIONS Thermal Resistance Junction to Ambient RJA Pad Area = 0.76 in2 (490.3 mm2) (Note 2) Pad Area = 0.027 in2 (17.4 mm2) (Figure 23) Pad Area = 0.006 in2 (3.87 mm2) (Figure 23) SWITCHING SPECIFICATIONS (VGS = 4.5V) Turn-On Time Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Turn-Off Time tON td(ON) tr td(OFF) tf tOFF tON td(ON) tr td(OFF) tf tOFF Qg(TOT) Qg(5) Qg(TH) Qgs Qgd CISS COSS CRSS VDS = 25V, VGS = 0V, f = 1MHz (Figure 13) VGS = 0V to 10V VGS = 0V to 5V VGS = 0V to 1V VDD = 30V, ID = 1.0A, Ig(REF) = 1.0mA (Figures 14, 19, 20) VDD = 30V, ID = 3.8A VGS = 10V, RGS = 30 (Figures 16, 21, 22) VDD = 30V, ID = 1.0A VGS = 4.5V, RGS = 27 (Figures 15, 21, 22) 8 30 25 25 57 75 ns ns ns ns ns ns 50 191 228
oC/W oC/W oC/W
TA = 25oC, Unless Otherwise Specified SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
60 55 -
-
1 250 100
V V A A nA
VGS = 16V
1 -
0.075 0.088 0.092
3 0.090 0.105 0.110
V
SWITCHING SPECIFICATIONS (VGS = 10V) Turn-On Time Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Turn-Off Time GATE CHARGE SPECIFICATIONS Total Gate Charge Gate Charge at 5V Threshold Gate Charge Gate to Source Gate Charge Gate to Drain "Miller" Charge CAPACITANCE SPECIFICATIONS Input Capacitance Output Capacitance Reverse Transfer Capacitance 330 100 18 pF pF pF 9.4 5.3 0.42 1.05 2.4 11.2 6.4 0.5 nC nC nC nC nC 5 11 46 31 24 116 ns ns ns ns ns ns
Source to Drain Diode Specifications
PARAMETER Source to Drain Diode Voltage SYMBOL VSD trr QRR ISD = 3.8A ISD = 1.0A Reverse Recovery Time Reverse Recovered Charge ISD = 1.0A, dISD/dt = 100A/s ISD = 1.0A, dISD/dt = 100A/s TEST CONDITIONS MIN TYP MAX 1.25 1.00 48 89 UNITS V V ns nC
(c)2001 Fairchild Semiconductor Corporation
HUFA76407DK8 Rev. B
HUFA76407DK8 Typical Performance Curves
1.2 POWER DISSIPATION MULTIPLIER 1.0 0.8 0.6 0.4 0.2 0 0 25 50 75 100 125 150 TA , AMBIENT TEMPERATURE (oC) 0 25 50 75 100 125 150 TA, AMBIENT TEMPERATURE (oC) 4 VGS = 10V, RJA = 50oC/W 3
ID, DRAIN CURRENT (A)
2
1 VGS = 4.5V, RJA = 228oC/W
FIGURE 1. NORMALIZED POWER DISSIPATION vs AMBIENT TEMPERATURE
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs AMBIENT TEMPERATURE
2 1 THERMAL IMPEDANCE ZJA, NORMALIZED DUTY CYCLE - DESCENDING ORDER 0.5 0.2 0.1 0.05 0.02 0.01 PDM t1 t2 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZJA x RJA + TA 10-2 10-1 100 101 102 103 RJA = 228oC/W
0.1
0.01
SINGLE PULSE 0.001 10-5 10-4 10-3 t, RECTANGULAR PULSE DURATION (s)
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
200 100 IDM, PEAK CURRENT (A)
RJA = 228oC/W
TC = 25oC FOR TEMPERATURES ABOVE 25oC DERATE PEAK CURRENT AS FOLLOWS: I = I25 150 - TA 125
VGS = 5V 10
1
TRANSCONDUCTANCE MAY LIMIT CURRENT IN THIS REGION 10-4 10-3 10-2 10-1 t, PULSE WIDTH (s) 100 101 102 103
10-5
FIGURE 4. PEAK CURRENT CAPABILITY
(c)2001 Fairchild Semiconductor Corporation
HUFA76407DK8 Rev. B
HUFA76407DK8 Typical Performance Curves
500 RJA = 228oC/W ID, DRAIN CURRENT (A) 100
(Continued)
50 IAS, AVALANCHE CURRENT (A) SINGLE PULSE TJ = MAX RATED TA = 25oC If R = 0 tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD) If R 0 tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1] 10 STARTING TJ = 25oC STARTING TJ = 150oC
10 OPERATION IN THIS AREA MAY BE LIMITED BY rDS(ON)
100s
1ms 10ms
1
0.1 1 10 VDS, DRAIN TO SOURCE VOLTAGE (V) 100 200
1 0.01 0.1 1 10
tAV, TIME IN AVALANCHE (ms)
NOTE: Refer to Fairchild Application Notes AN9321 and AN9322. FIGURE 5. FORWARD BIAS SAFE OPERATING AREA FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING CAPABILITY
20
PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX VDD = 15V TJ = -55oC
20 VGS = 10V ID, DRAIN CURRENT (A) TJ = 25oC VGS = 5V 15 VGS = 4V 10 VGS = 3.5V PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX TA = 25oC VGS = 3V 4 VGS = 4.5V
ID, DRAIN CURRENT (A)
15
TJ = 150oC 10
5
5
0 2.0 2.5 3.0 3.5 4.5 4.0 VGS, GATE TO SOURCE VOLTAGE (V) 5.0
0 0 1 2 3 VDS, DRAIN TO SOURCE VOLTAGE (V)
FIGURE 7. TRANSFER CHARACTERISTICS
FIGURE 8. SATURATION CHARACTERISTICS
150 rDS(ON), DRAIN TO SOURCE ON RESISTANCE (m)
2.0 NORMALIZED DRAIN TO SOURCE ON RESISTANCE PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX ID = 3.8A PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX
VGS = 10V, ID = 3.8A
120
1.5
ID = 1A 90
1.0
60 2 3 5 7 4 6 8 VGS, GATE TO SOURCE VOLTAGE (V) 9 10
0.5 -80 -40 0 40 80 120 TJ, JUNCTION TEMPERATURE (oC) 160
FIGURE 9. DRAIN TO SOURCE ON RESISTANCE vs GATE VOLTAGE AND DRAIN CURRENT
FIGURE 10. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE
(c)2001 Fairchild Semiconductor Corporation
HUFA76407DK8 Rev. B
HUFA76407DK8 Typical Performance Curves
1.2 NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE VGS = VDS, ID = 250A NORMALIZED GATE THRESHOLD VOLTAGE
(Continued)
1.2 ID = 250A
1.0
1.1
0.8
1.0
0.6 -80 -40 0 40 80 120 160 T J, JUNCTION TEMPERATURE (oC)
0.9 -80 -40 0 40 80 120 160 TJ , JUNCTION TEMPERATURE (oC)
FIGURE 11. NORMALIZED GATE THRESHOLD VOLTAGE vs JUNCTION TEMPERATURE
FIGURE 12. NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE vs JUNCTION TEMPERATURE
10
1000 CISS = CGS + CGD C, CAPACITANCE (pF)
VGS , GATE TO SOURCE VOLTAGE (V)
VDD = 30V 8
6
100 COSS CDS + CGD
4 WAVEFORMS IN DESCENDING ORDER: ID = 3.8A ID = 1.0A 0 2 4 6 Qg, GATE CHARGE (nC) 8 10
2
10 VGS = 0V, f = 1MHz 5 0.1 1.0
CRSS = CGD
0 10 60
VDS , DRAIN TO SOURCE VOLTAGE (V)
NOTE: Refer to Fairchild Application Notes AN7254 and AN7260. FIGURE 14. GATE CHARGE WAVEFORMS FOR CONSTANT GATE CURRENT
FIGURE 13. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
50 VGS = 4.5V, VDD = 30V, ID = 1.0A SWITCHING TIME (ns) 40 tf 30 td(OFF) tr SWITCHING TIME (ns)
80 VGS = 10V, V DD = 30V, ID = 3.8A td(OFF)
60 tf 40
20 td(ON) 10
20
tr td(ON)
0 0 10 20 30 40 RGS, GATE TO SOURCE RESISTANCE () 50
0 0 10 20 30 40 RGS, GATE TO SOURCE RESISTANCE () 50
FIGURE 15. SWITCHING TIME vs GATE RESISTANCE
FIGURE 16. SWITCHING TIME vs GATE RESISTANCE
(c)2001 Fairchild Semiconductor Corporation
HUFA76407DK8 Rev. B
HUFA76407DK8 Test Circuits and Waveforms
VDS BVDSS L VARY tP TO OBTAIN REQUIRED PEAK IAS VGS DUT tP RG IAS VDD tP VDS VDD
+
0V
IAS 0.01
0 tAV
FIGURE 17. UNCLAMPED ENERGY TEST CIRCUIT
FIGURE 18. UNCLAMPED ENERGY WAVEFORMS
VDS RL VDD VDS VGS = 10V VGS
+
Qg(TOT)
Qg(5) VDD VGS VGS = 1V 0 Qg(TH) Qgs Ig(REF) 0 Qgd VGS = 5V
DUT Ig(REF)
FIGURE 19. GATE CHARGE TEST CIRCUIT
FIGURE 20. GATE CHARGE WAVEFORMS
VDS
tON td(ON) RL VDS
+
tOFF td(OFF) tr tf 90%
90%
VGS
VDD DUT 0
10% 90%
10%
RGS VGS VGS 0 10% 50% PULSE WIDTH 50%
FIGURE 21. SWITCHING TIME TEST CIRCUIT
FIGURE 22. SWITCHING TIME WAVEFORM
(c)2001 Fairchild Semiconductor Corporation
HUFA76407DK8 Rev. B
HUFA76407DK8 Thermal Resistance vs. Mounting Pad Area
The maximum rated junction temperature, TJM, and the thermal resistance of the heat dissipating path determines the maximum allowable device power dissipation, PDM, in an application. Therefore the application's ambient temperature, TA (oC), and thermal resistance RJA (oC/W) must be reviewed to ensure that T JM is never exceeded. Equation 1 mathematically represents the relationship and serves as the basis for establishing the rating of the part. inches is the top copper area including the gate and source pads.
R JA = 103.2 - 24.3 x
300 RJA = 103.2 - 24.3 250
ln ( Area )
* ln(AREA)
(EQ. 2)
228 oC/W - 0.006in2 191 oC/W - 0.027in2
R, RJA (oC/W)
200 150 100 50
P
(T -T ) JM A DM = -----------------------------R JA
(EQ. 1
R = 46.4 - 21.7 * ln(AREA)
In using surface mount devices such as the SOP-8 package, the environment in which it is applied will have a significant influence on the part's current and maximum power dissipation ratings. Precise determination of PDM is complex and influenced by many factors: 1. Mounting pad area onto which the device is attached and whether there is copper on one side or both sides of the board. 2. The number of copper layers and the thickness of the board. 3. The use of external heat sinks. 4. The use of thermal vias. 5. Air flow and board orientation. 6. For non steady state applications, the pulse width, the duty cycle and the transient thermal response of the part, the board and the environment they are in. Fairchild provides thermal information to assist the designer's preliminary application evaluation. Figure 23 defines the RJA for the device as a function of the top copper (component side) area. This is for a horizontally positioned FR-4 board with 1oz copper after 1000 seconds of steady state power with no air flow. This graph provides the necessary information for calculation of the steady state junction temperature or power dissipation. Pulse applications can be evaluated using the Fairchild device Spice thermal model or manually utilizing the normalized maximum transient thermal impedance curve. Displayed on the curve are RJA values listed in the Electrical Specifications table. The points were chosen to depict the compromise between the copper board area, the thermal resistance and ultimately the power dissipation, PDM. Thermal resistances corresponding to other copper areas can be obtained from Figure 23 or by calculation using Equation 2. RJA is defined as the natural log of the area times a cofficient added to a constant. The area, in square The thermal coupling resistance vs. copper area is also graphically depicted in Figure 23. It is important to note the thermal resistance (RJA) and thermal coupling resistance (R) are equivalent for both die. For example at 0.1 square inches of copper: RJA1 = RJA2 = 159oC/W
0 0.001 0.01 0.1 1 AREA, TOP COPPER AREA (in2) PER DIE
FIGURE 23. THERMAL RESISTANCE vs MOUNTING PAD AREA
While Equation 2 describes the thermal resistance of a single die, several of the new UltraFETs are offered with two die in the SOP-8 package. The dual die SOP-8 package introduces an additional thermal component, thermal coupling resistance, R. Equation 3 describes R as a function of the top copper mounting pad area.
R
= 46.4 - 21.7 x
ln ( Area )
(EQ. 3)
R1 = R2 = 97oC/W
TJ1 and TJ2 define the junction temerature of the respective die. Similarly, P1 and P2 define the power dissipated in each die. The steady state junction temperature can be calculated using Equation 4 for die 1and Equation 5 for die 2. Example: To calculate the junction temperature of each die when die 2 is dissipating 0.5 Watts and die 1 is dissipating 0 Watts. The ambient temperature is 70oC and the package is mounted to a top copper area of 0.1 square inches per die. Use Equation 4 to calulate T J1 and and Equation 5 to calulate TJ2.
.
(EQ. 4) J1 = P 1 R JA + P 2 R + T A oC/W) + (0.5 Watts)(97 oC/W) + 70oC TJ1 = (0 Watts)(159 TJ1 = 119oC T
(c)2001 Fairchild Semiconductor Corporation
HUFA76407DK8 Rev. B
HUFA76407DK8
T J2 = P 2 R JA + P 1 R + T A (EQ. 5) oC/W) + (0 Watts)(97oC/W) + 70C TJ2 = (0.5 Watts)(159
graph. Spice and SABER thermal models are provided for each of the listed pad areas. Copper pad area has no perceivable effect on transient thermal impedance for pulse widths less than 100ms. For pulse widths less than 100ms the transient thermal impedance is determined by the die and package. Therefore, CTHERM1 through CTHERM5 and RTHERM1 through RTHERM5 remain constant for each of the thermal models. A listing of the model component values is available in Table 1.
TJ2 = 150oC The transient thermal impedance (ZJA) is also effected by varied top copper board area. Figure 24 shows the effect of copper pad area on single pulse transient thermal impedance. Each trace represents a copper pad area in square inches corresponding to the descending list in the
160 COPPER BOARD AREA - DESCENDING ORDER 0.020 in2 0.140 in2 0.257 in2 0.380 in2 0.493 in2
IMPEDANCE (oC/W)
ZJA, THERMAL
120
80
40
0 10-1 100 101 t, RECTANGULAR PULSE DURATION (s) 102 103
FIGURE 24. THERMAL RESISTANCE vs MOUNTING PAD AREA
(c)2001 Fairchild Semiconductor Corporation
HUFA76407DK8 Rev. B
HUFA76407DK8 PSPICE Electrical Model
.SUBCKT HUFA76407DK8 2 1 3 ;
CA 12 8 4.55e-10 CB 15 14 5.20e-10 CIN 6 8 3.11e-10
REV 28 May 1999
DBODY 7 5 DBODYMOD DBREAK 5 11 DBREAKMOD DPLCAP 10 5 DPLCAPMOD
10
LDRAIN DPLCAP 5 RLDRAIN DBREAK 11 + EBREAK MWEAK MMED MSTRO CIN LSOURCE 8 RSOURCE RLSOURCE S1A 12 S1B CA 13 + EGS 6 8 EDS 13 8 S2A 14 13 S2B CB + 5 8 14 IT 15 17 RBREAK 18 RVTEMP 19 7 SOURCE 3 17 18 DBODY DRAIN 2 RSLC1 51 ESLC 50
RSLC2
5 51
ESG 6 8 + LGATE GATE 1 RLGATE EVTEMP RGATE + 18 22 9 20 EVTHRES + 19 8 6
IT 8 17 1 LDRAIN 2 5 1.0e-9 LGATE 1 9 1.5e-9 LSOURCE 3 7 4.86e-10 MMED 16 6 8 8 MMEDMOD MSTRO 16 6 8 8 MSTROMOD MWEAK 16 21 8 8 MWEAKMOD RBREAK 17 18 RBREAKMOD 1 RDRAIN 50 16 RDRAINMOD 3.00e-2 RGATE 9 20 3.37 RLDRAIN 2 5 10 RLGATE 1 9 15 RLSOURCE 3 7 4.86 RSLC1 5 51 RSLCMOD 1e-6 RSLC2 5 50 1e3 RSOURCE 8 7 RSOURCEMOD 3.80e-2 RVTHRES 22 8 RVTHRESMOD 1 RVTEMP 18 19 RVTEMPMOD 1 S1A S1B S2A S2B 6 12 13 8 S1AMOD 13 12 13 8 S1BMOD 6 15 14 13 S2AMOD 13 15 14 13 S2BMOD
-
-
VBAT 22 19 DC 1 ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*105),2))} .MODEL DBODYMOD D (IS = 3.17e-13 RS = 2.21e-2 TRS1 = 6.25e-4 TRS2 = -1.11e-6 CJO = 6.82e-10 TT = 7.98e-8 M = 0.65) .MODEL DBREAKMOD D (RS = 3.36e- 1TRS1 = 1.25e- 4TRS2 = 1.34e-6) .MODEL DPLCAPMOD D (CJO = 2.91e-1 0IS = 1e-3 0 = 0.85) M .MODEL MMEDMOD NMOS (VTO = 2.00 KP = 1 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 3.37) .MODEL MSTROMOD NMOS (VTO = 2.33 KP = 19 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u) .MODEL MWEAKMOD NMOS (VTO = 1.71 KP = 0.02 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 33.7 RS = 0.1) .MODEL RBREAKMOD RES (TC1 = 1.06e- 3TC2 = 0) .MODEL RDRAINMOD RES (TC1 = 1.23e-2 TC2 = 2.58e-5) .MODEL RSLCMOD RES (TC1 = 1.0e-3 TC2 = 1.0e-6) .MODEL RSOURCEMOD RES (TC1 = 0 TC2 = 0) .MODEL RVTHRESMOD RES (TC1 = -2.19e-3 TC2 = -4.97e-6) .MODEL RVTEMPMOD RES (TC1 = -1.11e- 3TC2 = 0) .MODEL S1AMOD VSWITCH (RON = 1e-5 .MODEL S1BMOD VSWITCH (RON = 1e-5 .MODEL S2AMOD VSWITCH (RON = 1e-5 .MODEL S2BMOD VSWITCH (RON = 1e-5 .ENDS ROFF = 0.1 ROFF = 0.1 ROFF = 0.1 ROFF = 0.1 VON = -7.0 VOFF= -2.5) VON = -2.5 VOFF= -7.0) VON = -1.0 VOFF= 0) VON = 0 VOFF= -1.0)
NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley.
(c)2001 Fairchild Semiconductor Corporation
+
-
EBREAK 11 7 17 18 67.8 EDS 14 8 5 8 1 EGS 13 8 6 8 1 ESG 6 10 6 8 1 EVTHRES 6 21 19 8 1 EVTEMP 20 6 18 22 1
RDRAIN 21 16
-
VBAT +
8 22 RVTHRES
HUFA76407DK8 Rev. B
HUFA76407DK8 SABER Electrical Model
REV 28May 1999 template HUFA76407dk8 n2,n1,n3 electrical n2,n1,n3 { var i iscl d..model dbodymod = (is = 3.17e-13, cjo = 6.82e-10, tt = 7.98e-8, m = 0.65) d..model dbreakmod = () d..model dplcapmod = (cjo = 2.91e-10, is = 1e-30, m = 0.85) m..model mmedmod = (type=_n, vto = 2.00, kp = 1, is = 1e-30, tox = 1) m..model mstrongmod = (type=_n, vto = 2.33, kp = 19, is = 1e-30, tox = 1) m..model mweakmod = (type=_n, vto = 1.71, kp = 0.02, is = 1e-30, tox = 1) sw_vcsp..model s1amod = (ron = 1e-5, roff = 0.1, von = -7, voff = -2.5) sw_vcsp..model s1bmod = (ron =1e-5, roff = 0.1, von = -2.5, voff = -7) sw_vcsp..model s2amod = (ron = 1e-5, roff = 0.1, von = -1.0, voff = 0) sw_vcsp..model s2bmod = (ron = 1e-5, roff = 0.1, von = 0, voff = -1) c.ca n12 n8 = 4.55e-10 c.cb n15 n14 = 5.20e-10 c.cin n6 n8 = 3.11e-10 d.dbody n7 n71 = model=dbodymod d.dbreak n72 n11 = model=dbreakmod d.dplcap n10 n5 = model=dplcapmod i.it n8 n17 = 1 l.ldrain n2 n5 = 1e-9 l.lgate n1 n9 = 1.5e-9 l.lsource n3 n7 = 4.86e-10
GATE 1 RLGATE CIN LGATE
LDRAIN DPLCAP 10 RSLC1 51 RSLC2 ISCL RLDRAIN RDBREAK 72 DBREAK 11 MWEAK MMED MSTRO 8 EBREAK + 17 18 71 RDBODY 5 DRAIN 2
ESG + EVTEMP RGATE + 18 22 9 20 6 6 8 EVTHRES + 19 8
50 RDRAIN 21 16
DBODY
m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u res.rbreak n17 n18 = 1, tc1 = 1.06e-3, tc2 = 0 res.rdbody n71 n5 = 2.21e-2, tc1 = -6.25e-4, tc2 = -1.11e-6 res.rdbreak n72 n5 = 3.36e-1, tc1 = 1.25e-4, tc2 = 1.34e-6 res.rdrain n50 n16 = 3.00e-2, tc1 = 1.23e-2, tc2 = 2.58e-5 res.rgate n9 n20 = 3.37 res.rldrain n2 n5 = 10 res.rlgate n1 n9 = 15 res.rlsource n3 n7 = 4.86 res.rslc1 n5 n51 = 1e-6, tc1 = 1e-3, tc2 = 1e-6 res.rslc2 n5 n50 = 1e3 res.rsource n8 n7 = 3.80e-2, tc1 = 0, tc2 = 0 res.rvtemp n18 n19 = 1, tc1 = -1.11e-3, tc2 = 0 res.rvthres n22 n8 = 1, tc1 = -2.19e-3, tc2 = -4.97e-6 spe.ebreak n11 n7 n17 n18 = 67.8 spe.eds n14 n8 n5 n8 = 1 spe.egs n13 n8 n6 n8 = 1 spe.esg n6 n10 n6 n8 = 1 spe.evtemp n20 n6 n18 n22 = 1 spe.evthres n6 n21 n19 n8 = 1 sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod v.vbat n22 n19 = dc=1 equations { i (n51->n50) +=iscl iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/105))** 2)) } }
S1A 12 13 8 S1B CA 13 + EGS 6 8 S2A 14 13 S2B
-
LSOURCE 7 RLSOURCE
SOURCE 3
RSOURCE RBREAK 17 18 RVTEMP CB + EDS 5 8 19 14 IT
15
VBAT +
-
-
8 RVTHRES
22
(c)2001 Fairchild Semiconductor Corporation
HUFA76407DK8 Rev. B
HUFA76407DK8 SPICE Thermal Model
REV 1June 1999 HUFA76407DK8 Copper Area = 0.02 in2 CTHERM1 th 8 8.5e-4 CTHERM2 8 7 1.8e-3 CTHERM3 7 6 5.0e-3 CTHERM4 6 5 1.3e-2 CTHERM5 5 4 4.0e-2 CTHERM6 4 3 9.0e-2 CTHERM7 3 2 4.0e-1 CTHERM8 2 tl 1.4 RTHERM1 th 8 3.5e-2 RTHERM2 8 7 6.0e-1 RTHERM3 7 6 2 RTHERM4 6 5 8 RTHERM5 5 4 18 RTHERM6 4 3 39 RTHERM7 3 2 42 RTHERM8 2 tl 48
RTHERM1 8 CTHERM1 th JUNCTION
RTHERM2 7
CTHERM2
RTHERM3 6
CTHERM3
RTHERM4 5
CTHERM4
SABER Thermal Model
Copper Area = 0.02 in2 template thermal_model th tl thermal_c th, tl { ctherm.ctherm1 th 8 = 8.5e-4 ctherm.ctherm2 8 7 = 1.8e-3 ctherm.ctherm3 7 6 = 5.0e-3 ctherm.ctherm4 6 5 = 1.3e-2 ctherm.ctherm5 5 4 = 4.0e-2 ctherm.ctherm6 4 3 = 9.0e-2 ctherm.ctherm7 3 2 = 4.0e-1 ctherm.ctherm8 2 tl = 1.4 rtherm.rtherm1 th 8 = 3.5e-2 rtherm.rtherm2 8 7 = 6.0e-1 rtherm.rtherm3 7 6 = 2 rtherm.rtherm4 6 5 = 8 rtherm.rtherm5 5 4 = 18 rtherm.rtherm6 4 3 = 39 rtherm.rtherm7 3 2 = 42 rtherm.rtherm8 2 tl = 48 }
RTHERM5 4
CTHERM5
RTHERM6 3
CTHERM6
RTHERM7 2
CTHERM7
RTHERM8
CTHERM8
tl
AMBIENT
TABLE 1. THERMAL MODELS COMPONENT CTHERM6 CTHERM7 CTHERM8 RTHERM6 RTHERM7 RTHERM8 0.02 in2 9.0e-2 4.0e-1 1.4 39 42 48 0.14 in2 1.3e-1 6.0e-1 2.5 26 32 35 0.257 in2 1.5e-1 4.5e-1 2.2 20 31 38 0.38 in2 1.5e-1 6.5e-1 3 20 29 31 0.493 in2 1.5e-1 7.5e-1 3 20 23 25
(c)2001 Fairchild Semiconductor Corporation
HUFA76407DK8 Rev. B
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Rev. H4

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